1. Field of the Invention
The present disclosure relates generally to electrical and electronic circuits and more specifically to prevention of leakage current during PAD overshoot and undershoot.
2. Description of Background
CMOS bi-directional interface circuits generally require some tolerance to voltage over/undershoots at a driver/receiver interface terminal, referred to herein as a PAD, caused by mismatch impedance between the output of the driver/receiver and the transmission line. Interface circuit electrical specifications often require a certain amount of over/undershoot tolerance be designed into the I/O. For example, the electrical specification for a Universal Serial Bus interface circuit requires an I/O operating between 0-3.3V to be capable of withstanding continuous exposure to a −1V to 4.6V signal.
Two unique problems occur in the driver circuit of an I/O when the PAD voltage extends beyond the supply rail voltages (i.e. VDD and GND). First, the drain-substrate or drain-nwell diodes can forward bias causing unwanted leakage current from PAD to VDD or from GND to PAD. Second, the transistors making up the output stage of the driver can turn on slightly even when the driver is supposed to be disabled (e.g., the driver is in receive mode).
FIG. 1 illustrates the output stage of a typical bidirectional driver. The gate nodes of the output FETs are controlled by pre-drive circuits that tune the rise and fall times of the driver signal. The PAD pin is the output of the driver and also the input of the receiver circuit (not shown). The I/O circuitry runs off a 3.3V power supply in this example. In the event of an overshoot, the PAD pin can reach 4.6V. The drain of the pFET rises to a higher potential than the n-well that is connected to VDD330 (3.3V). As a result, the PFET drain to well junction becomes forward biased, and current is allowed to flow from PAD to VDD330 supply. Similarly, in the event of an undershoot, the PAD pin can reach −1.0V. The drain of the NFET falls to a lower potential than the substrate that is connected to ground (0.0V). As a result, the NFET drain to substrate junction becomes forward biased, and current is allowed to flow from GND to PAD.
Specific to the case when the bi-directional I/O is in receive mode, the driver circuit should be disabled. From FIG. 1, this happens when both pull-up and pull-down transistors in the driver are cut off (i.e., the pFET gate is at 3.3V and the nFET gate is at 0.0V). As long as the PAD voltage does not extend beyond the supply rails, these transistors remain off. However, the output pFET in the driver will turn on slightly if the PAD experiences an overvoltage e.g., PAD goes up to 4.6V). This is because the pFET drain voltage exceeds the gate voltage. The result is unwanted current flow from PAD to VDD330 supply through the pFET. Similarly, the output nFET in the driver will turn on slightly if the PAD experiences an undervoltage (e.g., PAD goes to −1V). This is because the nFET gate voltage exceeds the drain voltage. The result is unwanted current flow from GND supply to PAD through the nFET.
Accordingly, a leakage current prevention scheme is needed.